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| Preliminary Data Sheet AS3510 Analog Audio Front-End Analog Voice Codec AS3510 AS14889 PRELIMINARY DATA SHEET PRELIMINARY DATA SHEET CONFIDENTIAL General Description This codec-chip contains a high performance 18 bit digital to analog converter. The dynamic range exceeds 95dB for best audio quality, for multi media applications (audio playback) within battery or line operated equipment. An additional audio power amplifier can directly drive external headphones or small 4 speakers with a power of up to half a watt. The power-up is click- and pop-less due to a smooth start-up circuitry. The overall distortion level is always below 0.02%. The microphone input amplifier contains an automatic gain control (AGC) with a dynamic range of 40dB to generate an amplified and compressed signal for the ADC, which provides 14 Bit resolution at 8kHz sampling-rate. Furthermore all necessary power management is included such as bandgap reference and four voltage regulators. The two 2.9V regulators are used internally (analog and digital supply), but can also be used for external purposes as well. The third output is designed to supply the peripheral cells and an external digital core, and is programmable from 1.75V to 2.5V in 4 steps (default is 2.5V). They are all powered through a DCDC-Converter, which can work down to a voltage of 1V. So the whole chip can work from a single battery cell. The fourth regulator is only used for generating the supply voltage for the analog USB 1.1 interface circuit. It is supplied via the USB connector. The performance of the regulators is excellent (noise, line- and load-regulation) and allows the direct supply of sensitive analog circuits. Because of the internal supply and signal filtering only few small external capacitors are required for de-coupling and stabilising and lead to very low output noise. The current consumption is very low and makes the chip ideally for battery powered devices. Key Features On chip DCDC Converter - 1.0 to 5.5V input voltage range Digital Supply, 2.9V Analog Supply, 2,9V Core Supply, 2.25V USB Transceiver Supply, 3.2V Dynamic range >95 dB THD < -85dB De-emphasis for 32 kHz, 44.1 kHz and 48 kHz Max. 2x 0.5W @ 4 Analog volume control -39dB to +3dB, 3dB steps including mute) Click- and pop-less startup and power down Auxiliary inputs for additional audio sources 14 Bit -ADC , 8kHz sampling rate Automatic gain control (AGC) 4 On-chip high performance voltage regulators - 18 Bit stereo DAC - Stereo power audio amplifier - Microphone input - - Low power consumption Wide battery supply range 1.0V - 5.5V Standard I2S interface Audio sampling rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, and 48 kHz I2C control interface USB 1.1 front-end 49 Pin BGA Package Applications - Audio frontend for cellular phones Stand alone MP3 player CD and DVD player PDAs www..com Rev. 0v3, Aug. 2002 CONFIDENTIAL Page 1 of 2 www..com www..com Figure 1 - - - - - - - - - - - - - - - - - - DUVDD VTRM D+ AUXR AUXL VSS VBAT1V SW Battery BVDD ENDCDC ENLDO12 - Rev. 0v3, Aug. 2002 100n 10u 100n 10u Block Diagram V_REG1 2,9V, 50mA @ BVDD=3V Preliminary Data Sheet AS3510 MICP Referenze Voltage & Current Generation BVDD MICN LDO1 - AGND VREF AVSS AVSS2 AVDD QLDO1 2,2u / 6,3V Z5U Block Diagram of AS3510 X X Gain Control +3...-39dB BVDD AVSS - - Microphon Amplifier BGND BVDD Interpolator *64 Multibit SD Modulator with DWA DAC + SC LPF 2nd Order SD ADC 14Bit, 8kHz + Interpolator Right Power Amplifier Dither Generation BVSS BVDD BVDD OUTR DVSS - c2,2u with RL=150 Ohm, or 330u with RL=8 Ohm SDO X Gain Control +3...-39dB CONFIDENTIAL Interpolator *64 Multibit SD Modulator with DWA DAC + SC LPF X Left Power Amplifier BVSS BVDD VTRM - Digital I2S Synchronisation BGND Buffer Pop-less Startup BVSS BVSS Headphone Jack BVDD OUTL LDO3 LDO2 AVSS MCLK - 2,2u with RL=150 Ohm, or 330u with RL=8 Ohm V_REG3 1,75V to 2.5V, 200mA @ BVDD=3V P Digital Audio Interface DCDC Converter USB 1.1 + LDO3.2V Single Ended to Differental Converter VP VM VPO VMO OEN RCV P USB Interface USB Connector 1 to 5.5V LRCK - SCLK - Serial Audio Interface (I2S) & Clock Generation QLDO3 PVDD 2,2u / 6,3V Z5U SDI - AVSS QLDO2 DVDD V_REG2 2,9V, 50mA @ BVDD=3V P Control Interface SCL - Control Interface (I2C Slave) SDA - PLDO3 2,2u / 6,3V Z5U Page 2 of 2 |
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